Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design

Abstract

Abstract The present reports an analytical modelling framework to provide insights into subthreshold logic design using metal-ferroelectric-metal–insulator-semiconductor (MFMIS) negative capacitance field effect transistor (NCFET). It is shown that the proposed model is effective in predicting supply voltage (V DD) dependent hysteresis as well as hysteresis-free voltage transfer characteristics (VTC) through the analytically obtained positive (hysteresis-free) and negative (hysteresis) values of gain (−dV O/dV IN) in NCFET based subthreshold inverter. The proposed subthreshold drain current model for NCFET has been extended to obtain closed-form analytical expressions of figures of merit of a subthreshold inverter such as nominal high and low output voltages, threshold logic voltage, and DC gain. The model while successfully capturing characteristics of MFMIS NCFETs is able to predict the occurrence of hysteresis in VTC due to negative differential resistance in the output characteristics of NCFET. Results show that an optimally designed MFMIS NCFET based inverter can achieve similar values of DC gain as exhibited by conventional MOSFET at ∼×(3–6) times lower supply voltages (V DD) along with an improvement in static and dynamic power dissipation. Results showcase an analytical modelling framework and its implications for reducing V DD for ultralow power subthreshold logic design with NCFETs.