High-performance voltage controlled multilevel MRAM cell

Abstract

Abstract In the recent past, spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic random access memories (MRAMs) have been studied for future energy efficient and non-volatile memory applications. Multilevel cell (MLC) design has emerged as one of the promising solutions to enhance the storage density of these MRAMs. However, the conventional MLC design adds a larger magnetic tunnel junction (MTJ) stack that makes it difficult to maintain low switching current and high speed. Moreover, it becomes very difficult to reduce the driver transistor size. This paper describes the application of voltage controlled magnetic anisotropy effect to design energy efficient and fast MLC MRAM cell. So far, this approach has been reported only in single-bit MTJ devices. In the proposed MLC the voltage control is able to reduce both SOT and STT switching currents. The results show that the voltage control in MLC enhances energy efficiency and switching speed by more than 80 times and 3 times, respectively, in comparison to conventional SOT based MLCs. The reduction in switching currents also achieves smaller transistor size and enhances area efficiency by 3.5% as compared to conventional SOT-MLC. The effect of different channel materials on SOT switching current has also been explored. Furthermore, the system level evaluation shows that voltage controlled MLC outperforms STT-MRAM and SOT-MRAM for designing cache memory.