Suppression of P-I-N forward leakage current in tunnel field-effect transistor

Abstract

Abstract In this paper, we propose a tunnel field-effect transistor (TFET) architecture for the suppression of P-I-N forward leakage current. The P-I-N forward leakage current is attributed to the drift-diffusion mechanism under the forward-bias condition; thereby, the gate loses all of its control over the channel. In the proposed device architecture, the source region is bifurcated into sub-regions (referred to as P+ and P++) with different p-type doping concentrations. We introduce an electrostatic source (ES) electrode over the oxide, which encapsulates the lowly doped (P+) source region. The ES is shorted to the source electrode, implying that a positive voltage at the source terminal causes the ES to turn positive, resulting in a decrement in the P+ characteristics in the source region. On the other hand, the increment in voltage causes the P+ source region to become an intrinsic region, thus minimizing the chances of the P-I-N diode becoming forward biased. In the proposed device architecture, by tuning the work function values of the ES, the P-I-N forward leakage current is suppressed by 3–6 orders of magnitude at the cost of the ON-state current loss of 3–10-fold of magnitude. Considering the detrimental impact of P-I-N forward leakage current in circuits, this small penalty on the part of the ON-state current is worth accepting for the significant reduction in parasitic P-I-N forward leakage current. We believe that the proposed technique will pave the way for widespread use of TFETs in logic circuits.