Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering

Abstract

Abstract An inner-gate engineered double gate heterostructure tunnel field effect transistor (SiGe/Si-IGTFET) has been presented. The inner-gate is grown at the center of the Si0.6Ge0.4/Si TFET, followed by a thin HfO2 dielectric layer. The drain current performance of the suggested device has been investigated comprehensively to discover its efficacy. The device provides much-lower ambipolarity (by 6 decades) compared to heterostructure TFET with a similar dimension. The SiGe/Si-IGTFET device has also shown higher immunity against short channel effects such as drain induced barrier lowering and gate induced drain leakage current (I GIDL). To examine the impact of inner-gate, various DC parameters such as ambipolar current (I amb), on current (I on), I on/I amb current ratio, average subthreshold swing (SS), surface potential, and electric field have been considered. The device offers a much improved current ratio (I on/I amb) of 1.78 × 1012 with an average SS of 23 mV decade−1 by optimizing the position and dielectric material of the inner-gate. The simulation of the suggested device is carried out using a 2D Silvaco Technology Computer-Aided Design (TCAD) device simulator.