1. SoC Solutions Builds FPGA System in record Time Using Synopsys’ ReadyIP Flow and CAST IPCores[J],2008
2. Design hardware calculator in PWM peripherals of nios II with Verilog HDL [J];Yang;Journal of Chongqing University of Posts and Telecommunications,2009
3. Pulse width modulation signal generator based on FPGA [J];Jianwei;Computer Engineering,2013