A Configurable High Speed Crossbar Network on FPGA

Abstract

Abstract The MPSoC platform plays a vital role in the design of parallel processor architectures. However, it poses a great challenge to design a configurable high-speed network regarding as the processors growing isomerization and reconfigurable. This paper proposes a configurable crossbar on-chip interconnection method based on FPGA, which can provide high speed high speed through Xilinx Fast Simplex Link (FSL) for processing elements include processors and hardware IP. We built a prototype system on FPGA to evaluate the transfer time and hardware costs of the crossbar network architectures. The experimental results show that each word can be reduced by 10 cycles, and the entire transmission delay only accounts for 6% of the total system operation time.