A Demodulation Circuit For Analog Front End Of Passive Tag Chip

Abstract

Abstract The demodulation circuit designed in this paper is suitable for the analog front end of passive UHF RFID tag chip, which can handle ASK signals with large changes in amplitude, modulation depth and signal frequency. Its performance meets the requirements of standards ISO/IEC 18000-6C and GB/T 29768-2013. Envelope detection circuit and limiter circuit are simple in structure and do not consume power. The comparison reference voltage is taken according to the average value of the envelope high and low levels, and is less affected by the dynamic changes of the input signal. Changing the width-to-length ratio of the MOSFETs in the feedback path of the comparator can adjust the hysteresis, with strong noise suppression and controllable sensitivity. The demodulator is implemented with TSMC 0.18 μm standard CMOS process. The simulation results show that the ASK signal modulation depth that the demodulator can handle is as low as 30%, and the maximum pulse width demodulation error is only 0.43%.