Investigation of a novel 5nm top bottom gated junctionless FinFET for improved switching and analog performance

Abstract

Abstract In this work, we have designed a Novel Top-Bottom Gated Junctionless (JL) Fin-Shaped Field Effect Transistor (FinFET) Structure. The main idea of designing this structure is to improve the output efficiency and reduce the Short Channel Effects (SCEs). This paper analyzes the Analog Performance of a Novel Junctionless FinFET Structure with 5nm Gate length investigated on Silvaco Atlas Technology Computer Aided Design (TCAD) Tools and compared to Conventional Junctionless Bulk FinFET Structure. This Novel JL FinFET has gates on both sides of the substrate, hence the name Top-Bottom Gated (TBG) FinFET. It is determined that the proposed novel device enhances the switching ratio by almost 100 times, hence improving the transconductance and output current. Our device also shows improvement in the output conductance over the conventional JL FinFET. The simulation results show that the Novel TBG JL FinFET structure has better ION/IOFF and thus reduces the short channel effects than the conventional bulk FinFET more effectively.