A high-precision time-to-digital converter applied to CDC

Abstract

Abstract This paper presents a high-precision CMOS time-to-digital converter (TDC) applied to a capacitance-to-digital converter (CDC). The time-to-digital converter in the capacitance-to-digital converter is used to measure the time interval between the charging time of the capacitor under test and the charging time of the internal reference capacitor. The time resolution of the TDC directly determines the capacitance resolution of the CDC. In order to improve the measurement resolution of TDC, a TDC structure based on phase-locked loop (PLL) is proposed. This paper first gives a capacitance-to-digital converter scheme, and then introduces the time-to-digital converter used in the scheme. The frequency multiplication technology of the phase-locked loop optimizes the integral nonlinearity (INL) of the interpolator and greatly improves the interpolation of the interpolation ratio. The TDC was realized in a 0.13-μm CMOS process, and the measurable time interval is 21.14μs. When the external reference clock is 200MHz, the resolution is 40.3ps and only 31 delay units are needed.