Design of a 5.94 FO4 absolute-value detector based on hybrid logic technique

Abstract

Abstract With the development of neural signal acquisition systems, spike sorting algorithms have become a hot topic in related fields. The delay of the spike detection system largely determines the speed of the overall signal acquisition system. This paper designs a low-delay Absolute-value Detector based on the GDI technique to improve the timeliness of the neural signal acquisition system. The final circuit has only 20 logic gates-56 transistors. According to the logical effort methodology, the final path delay is 5.94 FO4. This research can provide a reference for the design of future portable ultra-low delay neural signal acquisition systems.