Design and Optimization of A 4-bit Absolute-value Detector Using Half Adder and Comparator

Author:

Yao Xinyun

Abstract

Abstract In this paper, a design and optimization of a 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, and the traditional comparator, which can compare the two positive input values all expressed in binary form. To optimize the overall performance of the absolute value detector, this paper chooses to minimize the number of transistors and simplifies the circuit through logical analysis. As for calculating the overall delay and energy consumption, critical path identification is also studied and analyzed in this paper. Based on the theory of path effort and path parasitic delay, the grid capacitance and resistance are introduced into the calculation of inverter ratios. To achieve various optimization objectives, this study also combines the grid size and power supply voltage scaling techniques to reduce the delay and energy of the circuit, and finally finds the minimum energy loss at a 1.5x delay. The overall delay and energy can be expressed by the multiple of the unit size inverter of that. As a compromise, a minimum delay of 1.5 times is selected to reduce energy consumption by 39.16 %.

Publisher

IOP Publishing

Subject

Computer Science Applications,History,Education

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