VLSI architecture with a configurable data processing path based on serial distributed arithmetic

Abstract

Abstract The article considers the VLSI architecture intended for streaming data processing using a configurable path based on sequential distributed arithmetic. The development of specialized VLSIs is advisable if there is a need for serial production of devices, and the domain of application of such VLSIs decreases as the capabilities of the CPU, GPU and FPGA expand. The alternative approach is to build configurable VLSIs that can efficiently perform computations in related applications. The solution under consideration is focused on performing stream operations, including FIR filters and other tasks based on the operation “multiplication and accumulation”, for example, neural networks and deep learning algorithms. The architecture provides for compliance with the GALS (Globally Asynchronous, Locally Synchronous) approach, which allows placing many independent computing nodes in the VLSI. The characteristics of VLSI were evaluated and the areas of preferred application of the considered architecture were considered.