FPGA Implementation of Integer Loop Delay Estimation with Low Complexity in Undersampling Digital Predistortion System

Abstract

Abstract In a digital predistortion (DPD) system, accurate loop delay estimation is one of the prerequisites for precise calculation of the DPD coefficient. Multiplications of plural numbers are needed in most of the conventional loop delay estimation algorithms. Based on the Euclidean loop delay estimation (ELDE) method, this paper proposes a simplified Euclidean loop delay estimation (SELDE) method that can avoid the operation of the multiplication of plural numbers. The ELDE and SELDE method are implemented in actual undersampling systems, separately. The results of the experiments prove the feasibility and effectiveness of the methods. Compared with the ELDE method, the hardware resource consumption of SELDE is decreased, mainly reflected in the reduction of registers and look-up tables by 41.26% and 42.84%, respectively.