A 111dB-SNDR 20kHz-BW Delta-Sigma Modulator with Auto-Zeroing and Class-AB Amplifier

Abstract

Abstract This paper describes the design of a high-precision audio Delta-Sigma modulator. To guarantee the modulator linearity and resolution with a limited oversampling rate (OSR), 4th-order 1-bit architecture is chosen. Auto-zeroing technique is used to reduce offset and low-frequency noise. To optimize power consumption, the switched-capacitor loop filter is implemented by feedforward structure with a passive adder and class-AB two-stage amplifiers. A clock generator with optimized non-overlapping pulse widths is designed to improve precision. Simulation results in 180nm CMOS show that with a 10.24MHz sampling rate, the presented modulator achieves 111dB signal-to-noise-and-distortion ratio (SNDR) at 20kHz bandwidth (BW) and consumes 17.9mW power under 3.3V supply, corresponding to an excellent figure-of-merit (FoM) of 171.5dB. Simulation results in process corners and temperatures show that the modulator is robust over variations.