A 14-bit 1-GS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

Abstract

Abstract A 14-bit 1-GS/s Pipelined-Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 28-nm CMOS is presented in this paper. In the initial phase, a pair of SAR ADCs employing the Time-Interleaved (TI) technique are employed to attain the necessary sampling rate. A multi-comparators structure is used to increase the speed and improve the mismatch. We have implemented a foreground calibration technique to address capacitor mismatch, optimizing its processing logic to enhance the chip’s speed. The interstage operational amplifier adopts a two-stage structure. Some structural changes are presented to optimize its bandwidth and phase margin. A background calibration method for gain error is implemented. In the subsequent phase, we employ four SAR ADCs utilizing the TI method. The outcomes demonstrate that the ADC delivers a Signal-to-Noise and Distortion Ratio (SNDR) of 65.58 dB and a Spurious-Free Dynamic Range (SFDR) of 72.12 dB at a 1-GS/s sampling rate without calibration, and 69.02 dB SNDR and 81.26 dB SFDR at the same 1-GS/s sampling rate with calibration. The core layout occupies an area of 0.6 mm2 and consumes 225.02 mW of power.