Design of Low Parasitic Inductance SiC MOSFETs Halfbridge Power Modules

Abstract

Abstract The working mechanism of a half-bridge SiC MOSFETs two chips parallel module is studied. Its parasitic inductance of the power module is simulated by using the Ansoft Q3D Extractor software, and its heat transfer mechanism is simulated using the finite element software ANSYS software. Aiming at reducing the parasitic inductance, a new topology of power chips inside the module is designed, which places the chips that are in the same working circuit loop in close vicinity to reduce the whole circuit length and area. Meanwhile, the thermal characteristics are also analyzed. Considering the factors of parasitic inductance and heat dissipation, the optimal module design scheme is finally determined.