Abstract
Abstract
This research paper is dedicated to the design and optimization of a 4-bit Absolute-value Detector, with a specific focus on minimizing the delay and energy consumption inherent to the device. The primary function of this detector is to compare the absolute value of a 3-bit input, which ranges between −7 and +7, against a predetermined threshold value. Subsequently, the detector outputs a binary signal, either “1” or “0”, signifying whether the absolute magnitude of the input surpasses the set threshold. Based on the principle of operation, the detector is divided into three parts: a carry look-ahead adder, a 2-1 multiplexer and a comparator. After building the basic model, the critical path of this detector can be found. Therefore, the minimum delay and the energy can be obtained, as the delay equals to 82.1311 and the energy is 132.556. Then, by changing the V
DD
and size of the stage in this path, the energy can be optimized when delay becomes 1.5 times the minimum delay which equals to 123.2. As a result, both changing the two factors can make the energy become 24.95 and the energy reduction is 81%.