A Comparative Study on minimum skew Clock tree distribution algorithms for high-speed Digital Integrated Circuits

Abstract

Abstract In this paper an extensive analysis on clock tree synthesis algorithms are carried out with conventional cts, Mesh based cts, Meshless Multi-source and flexible H-tree multisource cts with mesh. The algorithms are analysed with industry standard placement benchmarks. Latency, clock power, wirelength, number of buffers, and clock skew are observed. The clock distribution algorithm which provides a single digit least skew is picked, the pros and cons of that algorithm is elaborately discussed.