Abstract
Abstract
In this study, a wearable electrocardiogram (ECG) acquisition system with high performance instrumentation amplifier is presented. It adopts a 3-op-amp circuit and utilizes 180nm CMOS technology to achieve large input impedance. Furthermore, a drive-right leg module is used to configure the input’s common-mode range, increasing the common-mode rejection rate. Simulations in standard 180nm CMOS technology show bandwidths ranging from 0.1Hz to 251Hz. The front-end circuit operates on a 0.8V power supply. At the same time, using LTspice to conduct a preliminary test on the performance of the circuit, the total integrated input-referred noise of the circuit is 3.98 µVRMS
, and the power consumption is 5.059 µ W . This satisfies the need for an ECG circuit with low power and noise requirements for wearable technology. The preliminary research findings presented in this paper have established a solid theoretical framework for the amplifier used in the measuring of ECG signals.
Subject
Computer Science Applications,History,Education
Reference12 articles.
1. A Review Of Wireless ECG Monitoring Systems Design;Alfarhan,2016
2. Design of Low-Power Low-noise CMOS ECG Amplifier for Smart Wearable Device;Yang;J. Phy. Conf. Series,2020
3. ECG Monitoring Systems: Review, Architecture, Processes, and Key Challenges;Mohamed;Sensors,2020
4. Design of ECG front end amplifier based on CMOS OTA;Zhang,2021