Design and Analysis of Four Port Router for Network-On-Chip Applications

Abstract

Abstract System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.