An investigation of performance and power efficiency for parallax background scrolling hardware written in high-level synthesis

Abstract

Abstract We are developing a game programming software library so that high-level synthesis, HLS, can automatically generate high-performance and low-power hardware modules. A mobile terminal with a user-available reconfigurable device like Field programmable gate array, FPGA, we have proposed will efficiently perform game application built in HLS-oriented game library instead of power-hungry software execution. The dynamic hardware reconfiguration on a single FPGA can execute many kinds of game applications. Our previous research has developed software description methods for two-background scrolling in HLS-oriented game programming library by using two methods. They are (1) Full-parallel equips plural physical ports loading background images individually making HLS hardware execute the entire process parallelly increasing the amount of hardware: (2) Semi-parallel shares the single port loading background images serially, suppressing the hardware growth while achieving moderate performance by overlapping operation phases. We investigate two methods about execution time and power efficiency on the parallax scrolling with 2 to 4 backgrounds. The execution times of full-parallel hardware at 100MHz clock frequency are constantly about 9.65 [ms] while those of semi-parallel are 28, 38 and 47 [ms]. The PC at 3.2 GHz shows 78, 98 and 105 [ms] respectively as well. The power efficiencies about the full-parallel estimated considering hardware enlargement are 167, 208 and 112 times compared to the software execution in the PC, while those of semi-parallel are 94, 88 and 75 times. This fact indicates that the full-parallel is better strategy for parallax background scrolling in this case although more hardware resource are invested.