Co-Design of a Low-Noise Amplifier and SPDT SW for Band 42 T/R Modules with Low NF, High Gain, and 50-ohm Matching in Bulk CMOS Technology

Abstract

Abstract The vast deployment of 5G communication system calls for low-cost, easy-to-integrate RF Front End Integrated Circuits (RFFE ICs) design. For better system performance, specific processes, such as SOI/GaN/GaAs, are widely used for RFFE receiver IC design. However, these specific processes are costly and hard to integrate with baseband ICs which are typically fabricated in bulk CMOS process. To overcome the high cost and integration challenges, this paper designed a Band 42 low-noise power amplifier (LNA) together with a single-pole double-throw switch (SDPT SW) in a 55nm bulk CMOS process. For the LNA, we integrated source degeneration inductance and gate-source capacitance feedback, which provides significant stability, matching and noise figure benefits. For LNA and SW co-optimization, we reduced the overall noise by reusing the input matching network. The B42 receiver’s minimum return loss(SW included) is better than -20dB, gain higher than 28dB, and the noise figure is better than 2.4dB; the switch’s off-state isolation is better than 30dB. To our knowledge, this B42 receiver RFFE design is the best combination of performance and cost in the Bulk CMOS process. This work demonstrated the possibility of fully integrating RFFE circuits in low cost bulk CMOS process with good performance.