Design of ECG Front End Amplifier Based on CMOS OTA

Abstract

Abstract The low-noise and low-power amplifier, an important part of ECG recordings, remains a vital challenge in the biomedical instrumentation amplifier field. This paper describe a method of using the capacitive feedback structure and the MOS-bipolar pseudo-resistor to reject the DC offset and amplify signals down to the milli-hertz range. This study used the noise efficiency factor (NEF) to quantify the tradeoff between power and noise. Fabricated in a 180 nm CMOS process, the amplifier consumes 1.44 µW, and achieves the input referred noise of 3.89 µVrms The calculated NEF is 18.07, while the corresponding to common-mode rejection ratio (CMRR) is 87.72 dB. The device achieves low-noise, low-power and appropriate CMRR, which provides a reference for the design of biomedical instrumentation amplifier.