Implementation of Fast Huffman Encoding Based on FPGA

Abstract

Abstract In order to improve the efficiency of JPEG encoding architecture, some imagine compression systems use pipeline technology. Different modules will spend different cycles in the image compression, so the pipeline is prone to blockage. This paper proposes uses doublebyte splicing output Huffman code architecture and double Huffman encoding units on FPGA, so that Huffman encoding process spent less clock cycles in JPEG encoding, and pipelined JPEG encoding algorithm can be encoded in real time without blocking. According to the FPGA verification, although the number of logic units used will increase, Huffman encoding takes less clock cycles.