Author:
Hao Muzhen,Liu Xiaodong,Liu Zhizhe,Ji Feng,Sun Di,Yin Hongjie,Li Xingwang
Abstract
Abstract
This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.
Subject
General Physics and Astronomy
Reference6 articles.
1. A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-µm CMOS Technology;Vaucher;IEEE JSSC,2000
2. A novel CML latch for ultra high speed applications;Zhang,2014
3. Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications;Luo;IEEE Transactions on Circuits and Systems II: Express Briefs,2015
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. VLSI Design for Low-power and Wide-band Programmable Frequency Divider;2023 IEEE 5th Eurasia Conference on IOT, Communication and Engineering (ECICE);2023-10-27
2. An mmWave Frequency Range Multi-Modulus Programmable Divider for FMCW Radar Applications;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01