A six-digit digital attenuator working in the Sub6G band

Abstract

Abstract A high-performance 3–6 GHz monolithic digital control attenuator chip is designed by using a 0.25 μm GaAs pHEMT process. The circuit adopts a cascade structure of 6 basic attenuation units, and 64 attenuation states are formed by controlling the on-state combination of different attenuation bits, and the attenuation structure connected in parallel to the attenuation resistor is given. The main simulation results show that the designed digitally controlled attenuator takes 0.5dB as the attenuation step, and the maximum attenuation value is 31.5 dB, an insertion loss of less than 2.55 dB, a return loss better than -15 dB, an attenuation accuracy of less than 0.5 dB for all states, an additional phase shift of less than -5°, a root mean square error better than 0.23 dB of attenuation amplitude, and chip size of 1.88 mm×1.0 mm.