An RSFQ flexible-precision multiplier utilizing bit-level processing

Abstract

Abstract An RSFQ flexible-precision multiplier is proposed. The circuit can perform multiplication with specified bit-width within a predefined bit range. The calculation bit-width can be changed in every operation. When the bit-width of a calculation decreases, the latency in cycles is reduced. The proposed circuit calculates the multiplication result with bit-level processing to save the circuit area. The circuit carries out multiplication by counting pulses on a signal line. An RSFQ flexible-precision matrix multiplication circuit based on the proposed multiplier is also proposed. Its internal multipliers share many component circuits and it is implemented in a compact area.