Power Efficient Technique for CMOS- Logic Circuits

Abstract

Abstract Power outages on normal CMOS circuit is very high it can be reduced by using the adiabatic technique. Adiabatic technique is used in the pull up part of CMOS logic. Power loss of CMOS Logic is in terms of heat. Adiabatic is an efficient technique where some of the energy stored in the load and it is used for next inputs without dissipating as heat. The adiabatic technique depends largely on the parameter variation. With the help of DSCH, MICROWIND, TANNER EDA (S-edit, TWV, TSP) Software’s power consumed by ECRL (Efficient Charge Recovery Logic) is compared to the power consumed by common CMOS for NAND and NOR inverter circuits. In this study it is find out that the adiabatic technique is the good choice rather than conventional technique in terms of power consumption.