High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Abstract

Abstract Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. This article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well recognised that the Decoder plays a crucial role. As part of the planned work in 22nm technology, a technique has been developed for evaluating the parameters Power delay product, Energy delay product, Power consumption, and Delay on 14T and 15T based employing 2 to 4 decoders based on MOSFET and GNRFET. So, the final proposed circuit is obtained by application of decoders with the use of GNRFET while improving the performance parameters.