Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

Abstract

Abstract 4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain carry adder (CCA). The whole circuit is concise and the critical path is rigorously considered to make it as short as possible. The delay is set to 1.5 times its minimum, which is positively corresponding to the length of the critical path, the energy accordingly reaches its lower limit. Gate sizing and Device Voltage (VDD) optimization are proceeded for the exact purpose of proving that the circuit energy is minimized.