Standard cell library design for edge computing chips

Abstract

Abstract With the rapid development of big data, IoT, and other technologies, edge computing has emerged, and the core of edge computing is the edge computing chip. To meet the rapidly growing data computing speed and data computing volume and taking into account the short design cycle and low cost, this paper proposes a standard cell library for designing edge computing chips based on the PDK of 0.13 μm SOI process. Compared with the existing edge computing chips that operate at 100 MHz, the edge computing chip designed with this cell library can operate at 1 GHz. The design process includes selecting cell types and heights for the cell library, designing and drawing circuit logic and layout, extracting characteristic parameters of the cell library, and verifying the cell functions. The validation results show the designed cell can operate at 1 GHz with low delay. Compared with a commercial device, the designed device has a higher operating frequency and realizes a good balance between area and power consumption, and the standard cell library has a good application prospect.