Capacitance characterization of silicon nanowires formed by cryogenic dry etching

Abstract

Abstract Arrays of silicon nanowires were fabricated by dry etching in the ICP mode in a mixture of SF6/O2 gases at a temperature of-140 °C. Defects located near the wafer surface with E a =0.30 eV, σ=(1–10)×10−14 cm2 and E a =0.68–0.74 eV, σ=1×10−15 cm2 were detected by admittance spectroscopy and deep-level transient spectroscopy. An increase in the dry etching time from 3.5 min (for the 1st sample) to 4.5 min (for the 2nd sample) leads to an rise of their concentration, but additional stage of wet etching in 4% KOH during 30 s leads to a vanish of the response from the first sample (N T ˂1011 cm−3), while for the second sample the defect concentration becomes in two times lower.