Formal Verification of ST Programs using CSP

Abstract

Abstract Programmable Logic Controllers (PLCs) are embedded devices that are widely used in industrial control systems. PLC programs are written in special languages that are defined in the IEC 61131-3 standard, which includes two textual and three graphical programming languages. Structured text (ST) language is one of IEC 61131-3 standards, which is a high-level text language similar to PASCAL language. ST language features the following advantages: freely programming style, compact structure and strong data processing capabilities. Using ST language can be more convenient to realize the complex control programs. In this paper, we research and discuss formal verification of PLC program based on ST language, and show the conversion rules from ST language to the formal modeling language named CSP# (short for Communicating Sequential Programs). Finally, a case study is presented to demonstrate the procedure that PLC programs written in ST language are translated into CSP#, consequently, and the result of verification is given using the Process Analysis Toolkit (PAT).