Interfacial charge associated reliability improvement in arsenide/antimonide tunneling interfaced-junctionless TFET

Abstract

Abstract This article focuses on the investigation of reliability improvement in the arsenide/antimonide tunable bandgap tunneling interfaced junctionless TFET (HD-HJLTFET) by introducing positive (donor) and negative (acceptor) localized interfacial trap charges (ITCs) at the semiconductor/oxide (S/O) and semiconductor/semiconductor (S/S) interface. The compound semiconducting materials, InAs (lower bandgap) and AlGaSb (higher bandgap) have been incorporated in the source and channel regions in the proposed device (HJLTFET). Further, to improve the device reliability against ITCs, a hetero dielectric engineered gated device has also been designed and analysed (HD-HJLTFET). In HD-HJLTFET, a high-k dielectric near source to channel (S/C) interface and low-k dielectric region towards drain to channel (D/C) interface has been used. It has been obtained that HD engineering enhances the microwave and harmonic distortion performance of HD-HJLTFET. It has been evaluated that HD-HJLTFET/ HJLTFET delivers ON current of 38.3 μA/14μA, transconductance 108 μS/23.2μS, cut-off frequency 805.8GHz/406.7GHz and gain of 223.5/197.4. Further results show that HD delivers gm2 (∼28% ↓), gm3 (∼9 times), second-order and third-order harmonic distortion (∼42% ↓ and ∼90% ↓), and total harmonic distortion (∼26% ↓) as compared to HJLTFET. The linearity parameters of HD-HJLTFET (VIP2, VIP3, IIP3, 1dB compression point, and IMD3) also showed marked improvement with negligible variation against different ITC polarity than its counter device, making it more reliable for low power microwave and distortion-free wireless communication systems.