Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor-Reference-Cited by-同舟云学术

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Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

Published:2014-01-20 Issue:01 Volume:9 Page:C01035-C01035
ISSN:1748-0221
Container-title:Journal of Instrumentation
language:
Short-container-title:J. Inst.

Author:

Anders G,Bertelsen H,Boisen A,Childers T,Dam M,Ellis N,Farthouat P,Ruiz C Gabaldon,Ghibaudi M,Gorini B,Haas S,Kaneda M,Ohm C,Oliveira M Silva,Pauly T,Pöttgen R,Schmieden K,Spiwoks R,Xella S

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Link

http://stacks.iop.org/1748-0221/9/i=01/a=C01035/pdf

Reference12 articles.

1. An FPGA based Topological Processor prototype for the ATLAS Level-1 Trigger upgrade

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation and performances of the IPbus protocol for the JUNO Large-PMT readout electronics;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2023-08

2. Commissioning of the new muon-to-central-trigger-processor interface at ATLAS;Journal of Instrumentation;2023-03-01

3. Integration and commissioning of the ATLAS Muon-to-Central-Trigger-Processor Interface for Run-3;Journal of Instrumentation;2022-04-01

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