Sector logic development for the ATLAS Level-0 muon trigger at HL-LHC

Abstract

Abstract The design of the Sector Logic (SL) for the ATLAS Level-0 muon trigger at the HL-LHC and the milestones achieved on the hardware and firmware developments are presented. The SL board includes an XCVU13P FPGA, FireFly transceivers, an IPMC mezzanine card developed by CERN, and a Mercury XU5 MPSoC mezzanine card. The first prototype of the SL board was produced, and all its functions have been verified. Fast tracking using Thin-Gap Chamber (TGC) hits, a core part of the Level-0 muon trigger for the endcap regions, has been developed for the full TGC detector coverage and the performance was confirmed with post-synthesis simulations. The processing of the TGC hits from ∼7000 channels has been demonstrated with a XCVU13P FPGA within ∼100 ns.