The design for test architecture in digital section of the ATLAS FE-I4 chip-Reference-Cited by-同舟云学术

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The design for test architecture in digital section of the ATLAS FE-I4 chip

Published:2011-01-17 Issue:01 Volume:6 Page:C01090-C01090
ISSN:1748-0221
Container-title:Journal of Instrumentation
language:
Short-container-title:J. Inst.

Author:

Zivkovic V,Schipper J -D,Kluit R,Garcia-Sciveres M,Mekkaoui A,Barbero M,Beccherle R,Gnani D,Hemperek T,Karagounis M,Menouni M,Fougeron D,Gensolen F,Gromov V,Kruth A,Darbo G,Fleury J,Clemens J -C,Dube S,Elledge D,Rozanov A,Arutinov D

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Reference6 articles.

1. Upset hardened memory design for submicron CMOS technology

2. A structured and scalable mechanism for test access to embedded reusable cores

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Production test engineering in FE-I4 system-on-chip to boost the reliability and high-quality demands in IBL applications;Journal of Instrumentation;2013-02-04

2. The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project;Journal of Instrumentation;2012-02-24

3. Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2011-09

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