SystemC framework for architecture modelling of electronic systems in future particle detectors

Abstract

Abstract The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in the industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications. This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, includes an event generator, interfaces with real physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy. This contribution details the structure of the framework and describes a case study based on the LHCb VeLo upgrade II.