A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade-Reference-Cited by-同舟云学术

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A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade

Published:2016-02-22 Issue:02 Volume:11 Page:C02063-C02063
ISSN:1748-0221
Container-title:Journal of Instrumentation
language:
Short-container-title:J. Inst.

Author:

Magalotti D.,Alunni L.,Biesuz N.,Bilei G.M.,Citraro S.,Crescioli F.,Fanò L.,Fedi G.,Magazzù G.,Servoli L.,Storchi L.,Palla F.,Placidi P.,Rossi E.,Spiezia A.

Publisher

IOP Publishing

Subject

Mathematical Physics,Instrumentation

Link

http://stacks.iop.org/1748-0221/11/i=02/a=C02063/pdf

Reference12 articles.

1. Associative Memory for L1 Track Triggering in LHC Environment

2. The Silicon Vertex Trigger upgrade at CDF

3. Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

4. A full mesh ATCA-based general purpose data processing board

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Coprocessor for the Fast Tracker Simulation;IEEE Transactions on Nuclear Science;2017-06

2. A fast and low-cost genotyping method for hepatitis B virus based on pattern recognition in point-of-care settings;Scientific Reports;2016-06-16

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