Single-line multi-voltage threshold method for scintillation detectors

Abstract

Abstract The multiple thresholds used in multi-voltage threshold (MVT) method provide more detailed information about the pulse amplitude of the input analog pulses than the simple time-over-threshold (TOT) method, thus allowing for better energy estimation and pulse reconstruction capabilities. However, as the number of thresholds increases, the number of comparators and digital signal readout channels required for MVT also increases. This requirement owing to the increased number of thresholds is the main disadvantage of MVT implementation using field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) because the FPGA resources required for TDC implementation are substantial and FPGAs have a limited number of input/output ports. Therefore, we propose a new single-line MVT method to improve the integrity of the FPGA-only data acquisition system without analog-to-digital converters by reducing the FPGA input channels required for the MVT method. The proposed method, which applies three different levels of thresholding, reduces the digital output signal line in the MVT by employing a 3-input XOR logic gate. The XOR gate integrates the output signals from the comparators and generates 1-bit line digital pulse train. We evaluated the energy performance of the proposed single-line MVT method using three different energy estimators. The energy estimates were compared with the ground truth energy calculated using domino-ring-sampler 4 (DRS4)-sampled analog pulses. The proposed method showed virtually equivalent energy resolution to that of DRS4-based pulse digitization method and better energy linearity than the conventional TOT method. Among the energy estimation methods used in single-line MVT, the crossing-point triangular sum method showed the best energy linearity. The proposed single-line MVT method will be useful when data acquisition systems without ADCs are implemented using FPGA-based TDCs. This is because the proposed method alleviates the problem of limited input ports and the numerous resources required for TDCs in FPGAs.