Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

Abstract

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.