Author:
Martinelli F.,Magliocca C.,Cardella R.,Charbon E.,Iacobucci G.,Nessi M.,Paolozzi L.,Rücker H.,Valerio P.
Abstract
Abstract
This paper presents a small-area monolithic pixel detector
ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of
the pre-shower detector of the FASER experiment at CERN. The purpose
of this prototype is to study the integration of fast front-end
electronics inside the sensitive area of the pixels and to identify
the configuration that could satisfy at best the specifications of
the experiment. Self-induced noise, instabilities and cross-talk
were minimised to cope with the several challenges associated to the
integration of pre-amplifiers and discriminators inside the pixels.
The methodology used in the characterisation and the design choices
will also be described. Two of the variants studied here will be
implemented in the pre-production ASIC of the FASER experiment
pre-shower for further tests.
Subject
Mathematical Physics,Instrumentation
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Two proposed BiCMOS inverters with enhanced performance;Ain Shams Engineering Journal;2024-01
2. The recent status of the FASER detector;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2022-10