A low power asynchronous column-parallel 10-bit analog to digital converter with a high input impedance

Abstract

Abstract This paper proposes a low power 10-bit asynchronous fully-differential column analog to digital converter (ADC) with successive approximation (SAR) and charge redistribution in a 180 nm SoI technology. The ADC is designed for use in Spacepix-2 monolithic active pixel sensor. A novel folded architecture of internal capacitive digital to analog converter (CDAC) is proposed. The total capacitance of CDAC is 512 fF, with a single unit capacitor capacitance only 0.5 fF and a size of 2.5 × 1.4 μm2. The total input capacitance of the proposed column ADC is only 220 fF. Two columns of a pixel matrix share a single ADC to double layout width. The layout area is 120 × 923 μm2. The sample rate is 4 MSps with power consumption of 225 μW from 1.8 V power supply.