SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD

Abstract

Abstract We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.