Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution

Abstract

Abstract We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.