Hardware design of the generic rear transition module for the global trigger system of the ATLAS phase II upgrade

Abstract

Abstract The High-Luminosity Large Hadron Collider is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the Large Hadron Collider Runs 1–3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of the trigger and data acquisition system. Global trigger is a new subsystem in the ATLAS phase-II upgrade, which will bring event filter-like capability to the level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture form factor named Global Common Module is proposed to be configured as processor nodes in the global trigger. To mitigate the risk and simplify the Global Common Module hardware design, a Generic Rear Transition Module is being developed. The Generic Rear Transition Module, which has been implemented with a Xilinx Versal Prime Field Programmable Gate Array and sufficient multi-gigabit transceivers, cannot only achieve system control and communication with the Front-End Link eXchange, but also provide additional processing or readout capacity.