Abstract
Abstract
As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In2Se3, at temperature as low as 400 °C. Top gate n-channel In2Se3 thin film transistors were fabricated with field-effect mobility ∼1 cm2 V−1 s−1, and simple polarization switching based memory results are presented.
Funder
National Science Foundation
U.S. Department of Energy
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science,General Chemistry
Cited by
6 articles.
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