Impact of Gate Offset in Gate Recess on DC and RF Performance of InAlAs/InGaAs InP-based HEMTs
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Published:2021-12-24
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ISSN:1674-1056
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Container-title:Chinese Physics B
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language:
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Short-container-title:Chinese Phys. B
Author:
Cao Shu-rui,Feng Rui-ze,Wang Bo,Liu Tong,Ding Peng,Jin Zhi
Abstract
Abstract
In this work, a set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, f
T decreased while f
max increased, and the highest f
max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usage.
Subject
General Physics and Astronomy