Power-efficient in vivo brain-machine interfaces via brain-state estimation

Abstract

Abstract Objective. Advances in brain–machine interfaces (BMIs) can potentially improve the quality of life of millions of users with spinal cord injury or other neurological disorders by allowing them to interact with the physical environment at their will. Approach. To reduce the power consumption of the brain-implanted interface, this article presents the first hardware realization of an in vivo intention-aware interface via brain-state estimation. Main Results. It is shown that incorporating brain-state estimation reduces the in vivo power consumption and reduces total energy dissipation by over 1.8× compared to those of the current systems, enabling longer better life for implanted circuits. The synthesized application-specific integrated circuit (ASIC) of the designed intention-aware multi-unit spike detection system in a standard 180 nm CMOS process occupies 0.03 mm2 of silicon area and consumes 0.63 µW of power per channel, which is the least power consumption among the current in vivo ASIC realizations. Significance. The proposed interface is the first practical approach towards realizing asynchronous BMIs while reducing the power consumption of the BMI interface and enhancing neural decoding performance compared to those of the conventional synchronous BMIs.