Integration of self-assembled carbon nanotube transistors: statistics and gate engineering at the wafer scale-Reference-Cited by-同舟云学术

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Integration of self-assembled carbon nanotube transistors: statistics and gate engineering at the wafer scale

Published:2006-09-22 Issue:20 Volume:17 Page:5038-5045
ISSN:0957-4484
Container-title:Nanotechnology
language:
Short-container-title:Nanotechnology

Author:

Marty L,Bonhomme A,Iaia A,André E,Rauwel E,Dubourdieu C,Toffoli A,Ducroquet F,Bonnot A M,Bouchiat V

Publisher

IOP Publishing

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Mechanics of Materials,General Materials Science,General Chemistry,Bioengineering

Link

http://stacks.iop.org/0957-4484/17/i=20/a=002/pdf

Reference35 articles.

1. Logic Circuits with Carbon Nanotube Transistors

2. An Integrated Logic Circuit Assembled on a Single Carbon Nanotube

3. High-κ dielectrics for advanced carbon-nanotube transistors and logic gates

4. Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes

5. High-density selective placement methods for carbon nanotubes

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1. Effect of Ti and Au buffer layers on controlling the density and wettability of well-aligned ZnO nanorod arrays grown on different substrates;Nanoscale Advances;2023

2. Effects of Parylene Coating on Electron Transport in Pristine Suspended Carbon Nanotube Field-Effect-Transistors;IEEE Transactions on Electron Devices;2014-10

3. Hydrothermal synthesis of nanostructured zinc oxide and study of their optical properties;Materials Research Bulletin;2012-03

4. Superhydrophobic surfaces via controlling the morphology of ZnO micro/nano complex structure;Chinese Physics B;2010-05

5. Nanoscale welding by AFM tip induced electric field;2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems;2009

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